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Senior analog mixed signal chip design engineer/design manager
Salary undisclosed
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Shanghai-Zhangjiang
5-10 years
master
45-75k-16 salary
Job introduction
Job Responsibilities:
1. Responsible for breaking through technical difficulties in the field of high-performance PLL/ADC chips and building a simulation design platform;
2. Responsible for demand decomposition, solution analysis and competitiveness improvement of related product development projects;
3. Responsible for the full process delivery of chip product development project design, tape-out, verification, small batch and mass production;
4. Responsible for improving the team's overall design and delivery capabilities in the field of high-performance PLL/ADC.
Job requirements:
1. Phd degree or above in microelectronics or related majors, more than 5 years of experience in high-performance PLL/ADC chip design and mass production,
2. Familiar with device models and basic circuit principles. Experience in behavioral modeling, mixed signal simulation and verification;
3. Be proficient in designing various basic modules of RF and simulation, and master the corresponding design platforms and software;
4. Understand the layout method of RF IC, and be familiar with SOI, SiGe, and CMOS processes;
5. Applicants who are familiar with various laboratory testing equipment and have experience in abnormal problem location and failure analysis will be given priority.
Job benefits
year-end bonus
stock options
performance bonus
Five insurances and one fund
Job promotion
Big room for development
Skills training
flexible working
Casual dining
5-10 years
master
45-75k-16 salary
Job introduction
Job Responsibilities:
1. Responsible for breaking through technical difficulties in the field of high-performance PLL/ADC chips and building a simulation design platform;
2. Responsible for demand decomposition, solution analysis and competitiveness improvement of related product development projects;
3. Responsible for the full process delivery of chip product development project design, tape-out, verification, small batch and mass production;
4. Responsible for improving the team's overall design and delivery capabilities in the field of high-performance PLL/ADC.
Job requirements:
1. Phd degree or above in microelectronics or related majors, more than 5 years of experience in high-performance PLL/ADC chip design and mass production,
2. Familiar with device models and basic circuit principles. Experience in behavioral modeling, mixed signal simulation and verification;
3. Be proficient in designing various basic modules of RF and simulation, and master the corresponding design platforms and software;
4. Understand the layout method of RF IC, and be familiar with SOI, SiGe, and CMOS processes;
5. Applicants who are familiar with various laboratory testing equipment and have experience in abnormal problem location and failure analysis will be given priority.
Job benefits
year-end bonus
stock options
performance bonus
Five insurances and one fund
Job promotion
Big room for development
Skills training
flexible working
Casual dining
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